Multiway FPGA partitioning by fully exploiting design hierarchy

Author:

Fang Wen-Jong1,Wu Allen C.-H.1

Affiliation:

1. Tsing Hua Univ., Taiwan

Abstract

In this paper, we present a new integrated synthesis and partitioning method for multiple-FPGA applications. Our approach bridges the gap between HDL synthesis and physical partitioning by fully exploiting the design hierarchy. We propose a novel multiple-FPGA synthesis and partitioning method which is performed in three phases: (1) fine-grained synthesis, (2) functional-based clustering, and (3) hierarchical set-covering partitioning. This method first synthesizes a design specification in a fine-grained way so that functional clusters can be preserved based on the structural nature of the design specification. Then, it applies a hierarchical set-covering partitioning method to form the final FPGA partitions. Experimental results on a number of benchmarks and industrial designs demonstrate that I/O limits are the bottleneck for CLB utilization when applying a traditional multiple-FPGA synthesis method on flattened netlists. In contrast, by fully exploiting the design structural hierarchy during the multiple-FPGA partitioning, our proposed method produces fewer FPGA partitions with higher CLB and lower I/O-pin utilizations.

Publisher

Association for Computing Machinery (ACM)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Computer Science Applications

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A Cluster-based Hierarchical Partitioning Approach for Multiple FPGAs;Journal of Computers;2014-09-01

2. Multi-FPGA Partitioning Method Based on Topological Levelization;Journal of Electrical and Computer Engineering;2010

3. A genetic algorithm high-level optimizer for complex datapath and data-flow digital systems;Applied Soft Computing;2007-06

4. FPGA Design Automation: A Survey;Foundations and Trends® in Electronic Design Automation;2006

5. Design hierarchy-guided multilevel circuit partitioning;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2003-04

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