1. High-level hierarchical HDL synthesis of pipelined FPGA-based circuits using synchronous modules;Maunder,1999
2. Efficient optimal design space characterization methodologies;Blythe;ACM Trans. Des. Automat. Electron. Syst.,2000
3. Statistical design space exploration for application-specific unit synthesis;Bruni,2001
4. Multiway FPGA partitioning by fully exploiting design hierarchy;Fang;ACM Trans. Des. Automat. Electron. Syst.,2000
5. Parameterized system design based on genetic algorithms;Ascia,2001