Affiliation:
1. University of Massachusetts Amherst, Amherst, MA
2. University of California Riverside, Riverside, CA
Abstract
Graphene is an emerging nanomaterial believed to be a potential candidate for post-Si nanoelectronics due to its exotic properties. Recently, a new
graphene nanoribbon crossbar
(xGNR) device was proposed which exhibits
negative differential resistance
(NDR). In this article, a multistate memory design is presented that can store multiple bits in a single cell enabled by this xGNR device, called
graphene nanoribbon tunneling random access memory
(GNTRAM). An approach to increase the number of bits per cell is explored alternative to physical scaling to overcome CMOS SRAM limitations. A comprehensive design for quaternary GNTRAM is presented as a baseline, implemented with a heterogeneous integration between graphene and CMOS. Sources of leakage and approaches to mitigate them are investigated. This design is extensively benchmarked against 16nm CMOS SRAMs and 3T DRAM. The proposed quaternary cell shows up to 2.27× density benefit versus 16nm CMOS SRAMs and 1.8× versus 3T DRAM. It has comparable read performance and is power efficient up to 1.32× during active period and 818× during standby against high-performance SRAMs. Multistate GNTRAM has the potential to realize high-density low-power nanoscale embedded memories. Further improvements may be possible by using graphene more extensively, as graphene transistors become available in the future.
Funder
Center for Hierarchical Manufacturing (CHM) at UMass Amherst
Focus Center Research Program (FCRP) Center on Functionally Engineering Nano Architectonics
Publisher
Association for Computing Machinery (ACM)
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Cited by
2 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献