1. Three-dimensional integrated circuits
2. Liu C , Zhang L , Han Y , Vertical interconnects squeezing in symmetric 3D mesh network-on-chip[C]//16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011 ). IEEE , 2011: 357-362. Liu C, Zhang L, Han Y, Vertical interconnects squeezing in symmetric 3D mesh network-on-chip[C]//16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011). IEEE, 2011: 357-362.
3. Networks-on-chip in a three-dimensional environment: A performance evaluation[J];Feero B S;IEEE Transactions on computers,2008
4. Syal N , Sehgal V K . Qualitative Analysis of 3D Routing Algorithms in 3× 3× 3 Mesh NoC Topology Under Varying Load in Bio-SoC[J] . International Journal of E-Health and Medical Communications (IJEHMC) , 2020 , 11(3): 86 - 102 . Syal N, Sehgal V K. Qualitative Analysis of 3D Routing Algorithms in 3× 3× 3 Mesh NoC Topology Under Varying Load in Bio-SoC[J]. International Journal of E-Health and Medical Communications (IJEHMC), 2020, 11(3): 86-102.
5. Khayambashi M , Yaghini P M , Eghbal A , Analytical reliability analysis of 3D NoC under TSV failure[J] . ACM Journal on Emerging Technologies in Computing Systems (JETC) , 2015 , 11(4): 1 - 16 . Khayambashi M, Yaghini P M, Eghbal A, Analytical reliability analysis of 3D NoC under TSV failure[J]. ACM Journal on Emerging Technologies in Computing Systems (JETC), 2015, 11(4): 1-16.