Beyond Static Parallel Loops: Supporting Dynamic Task Parallelism on Manycore Architectures with Software-Managed Scratchpad Memories-Reference-Cited by-同舟云学术

Beyond Static Parallel Loops: Supporting Dynamic Task Parallelism on Manycore Architectures with Software-Managed Scratchpad Memories

Published:2023-03-25 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 3
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Author:

Cheng Lin¹,Ruttenberg Max²,Jung Dai Cheol²,Richmond Dustin³,Taylor Michael²,Oskin Mark²,Batten Christopher¹

Affiliation:

1. Cornell University, USA

2. University of Washington, USA

3. University of California at Santa Cruz, Santa Cruz, USA

Funder

Defense Advanced Research Projects Agency

Air Force Research Laboratory

Publisher

ACM

Reference62 articles.

1. Tutu Ajayi , Khalid Al-Hawaj , Aporva Amarnath , Steve Dai , Scott Davidson , Paul Gao , Gai Liu , Atieh Lotfi , Julian Puscar , Anuj Rao , Austin Rovinski , Loai Salem , Ningxiao Sun , Christopher Torng , Luis Vega , Bandhav Veluri , Xiaoyang Wang , Shaolin Xie , Chun Zhao , Ritchie Zhao , Christopher Batten , Ronald G. Dreslinski , Ian Galton , Rajesh K. Gupta , Patrick P. Mercier , Mani Srivastava , Michael B. Taylor , and Zhiru Zhang . 2017 . Celerity: An Open-Source RISC-V Tiered Accelerator Fabric. Symp. on High Performance Chips (Hot Chips), Aug. Tutu Ajayi, Khalid Al-Hawaj, Aporva Amarnath, Steve Dai, Scott Davidson, Paul Gao, Gai Liu, Atieh Lotfi, Julian Puscar, Anuj Rao, Austin Rovinski, Loai Salem, Ningxiao Sun, Christopher Torng, Luis Vega, Bandhav Veluri, Xiaoyang Wang, Shaolin Xie, Chun Zhao, Ritchie Zhao, Christopher Batten, Ronald G. Dreslinski, Ian Galton, Rajesh K. Gupta, Patrick P. Mercier, Mani Srivastava, Michael B. Taylor, and Zhiru Zhang. 2017. Celerity: An Open-Source RISC-V Tiered Accelerator Fabric. Symp. on High Performance Chips (Hot Chips), Aug.

2. Tutu Ajayi , Khalid Al-Hawaj , Aporva Amarnath , Steve Dai , Scott Davidson , Paul Gao , Gai Liu , Anuj Rao , Austin Rovinski , Ningxiao Sun , Christopher Torng , Luis Vega , Bandhav Veluri , Shaolin Xie , Chun Zhao , Ritchie Zhao , Christopher Batten , Ronald G. Dreslinski , Rajesh K. Gupta , Michael B. Taylor , and Zhiru Zhang . 2017 . Experiences Using the RISC-V Ecosystem to Design an Accelerator-Centric SoC in TSMC 16nm . Workshop on Computer Architecture Research with RISC-V (CARRV), Oct. Tutu Ajayi, Khalid Al-Hawaj, Aporva Amarnath, Steve Dai, Scott Davidson, Paul Gao, Gai Liu, Anuj Rao, Austin Rovinski, Ningxiao Sun, Christopher Torng, Luis Vega, Bandhav Veluri, Shaolin Xie, Chun Zhao, Ritchie Zhao, Christopher Batten, Ronald G. Dreslinski, Rajesh K. Gupta, Michael B. Taylor, and Zhiru Zhang. 2017. Experiences Using the RISC-V Ecosystem to Design an Accelerator-Centric SoC in TSMC 16nm. Workshop on Computer Architecture Research with RISC-V (CARRV), Oct.

3. Runtime-Guided Management of Scratchpad Memories in Multicore Architectures

4. Performance of the CRAY T3E multiprocessor

5. The Design of OpenMP Tasks

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