High-Level Synthesis of Approximate Designs under Real-Time Constraints

Author:

Leipnitz Marcos T.1ORCID,Nazar Gabriel L.1

Affiliation:

1. Informatics Institute - Federal University of Rio Grande do Sul, Brazil

Abstract

The adoption of High-Level Synthesis (HLS) has increased as the latest HLS tools have evolved to provide high-quality results while improving productivity and time-to-market. Concurrently, many works have been proposing the incorporation of approximate computing techniques within HLS toolchains, allowing automated generation of inexact circuits for error-tolerant application domains with the aim of trading-off computation accuracy with area/power savings or performance improvements. Thus, when attempting to make a design meet timing requirements, designers of real-time systems using HLS may resort to approximation approaches. However, current approximate HLS tools do not allow specifying real-time constraints, being instead error-constrained to explore area, power, or performance optimizations. In this work, we propose an approximate HLS framework for real-time systems that can be integrated with state-of-the-art HLS tools. With this framework designers can specify real-time constraints and satisfy them while minimizing the output error. It uses scheduling information and Worst-Case Execution Time (WCET) analysis for iteratively exploring time-error trade-offs of approximations in the time-critical execution path. Experimental results on signal and image processing benchmarks show that we can reduce the WCET of exact designs by up to 35% with acceptable quality degradation.

Funder

Fundação de Amparo à Pesquisa do Estado do Rio Grande do Sul

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior

Conselho Nacional de Desenvolvimento Científico e Tecnológico

Publisher

Association for Computing Machinery (ACM)

Subject

Hardware and Architecture,Software

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1. LegUp

2. Enabling high-level synthesis resource sharing design space exploration in FPGAs through automatic internal bitwidth adjustments;Schafer B. Carrion;IEEE Trans. Comput.-Aided Design Integr. Circuits Syst.,2017

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