Affiliation:
1. Department of Electrical Engineering and Computer Science, Stanford University
Abstract
Most new computer architectures are concerned with maximizing performance by providing suitable instruction sets for compiled code and providing support for systems functions. We argue that the most effective design methodology must make simultaneous tradeoffs across all three areas: hardware, software support, and systems support. Recent trends lean towards extensive hardware support for both the compiler and operating systems software. However, consideration of all possible design tradeoffs may often lead to less hardware support. Several examples of this approach are presented, including: omission of condition codes, word-addressed machines, and imposing pipeline interlocks in software. The specifics and performance of these approaches are examined with respect to the MIPS processor.
Publisher
Association for Computing Machinery (ACM)
Reference12 articles.
1. Baskett F. Puzzle: an informal compute bound benchmark. Widely circulated and run. Baskett F. Puzzle: an informal compute bound benchmark. Widely circulated and run.
2. MIPS: A VLSI Processor Architecture
3. Code generation and reorganization in the presence of pipeline constraints
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