A practical tile size selection model for affine loop nests
Author:
Affiliation:
1. Indian Institute of Science
2. NVIDIA
3. Birla Institute of Technology and Science, Pilani
Funder
Science and Engineering Research Board
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/3447818.3462213
Reference41 articles.
1. Optimizing matrix multiply using PHiPAC
2. A practical automatic polyhedral parallelizer and locality optimizer
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1. Tile Size and Loop Order Selection using Machine Learning for Multi-/Many-Core Architectures;Proceedings of the 38th ACM International Conference on Supercomputing;2024-05-30
2. DHTS: A Dynamic Hybrid Tiling Strategy for Optimizing Stencil Computation on GPUs;IEEE Transactions on Computers;2023-10
3. Loop interchange and tiling for multi-dimensional loops to minimize write operations on NVMs;Journal of Systems Architecture;2023-02
4. A Methodology for Efficient Tile Size Selection for Affine Loop Kernels;International Journal of Parallel Programming;2022-05-23
5. Optimal Loop Tiling for Minimizing Write Operations on NVMs with Complete Memory Latency Hiding;2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC);2022-01-17
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