Multi Replica Bitline Delay Technique for Variation Tolerant Timing of SRAM Sense Amplifiers
Author:
Affiliation:
1. Oklahoma State University, Stillwater, OK, USA
Funder
National Science Foundation
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/2742060.2742065
Reference14 articles.
1. International technology roadmap for semiconductors. Technical report. http://public.itrs.net/. International technology roadmap for semiconductors. Technical report. http://public.itrs.net/.
2. A replica technique for wordline and sense control in low-power SRAM's
3. Variation-tolerant SRAM sense-amplifier timing using configurable replica bitlines
4. Low-power CMOS digital design
5. Simple Statistical Analysis Techniques to Determine Optimum Sense Amp Set Times
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1. A Novel Decoder Design for Logic Computation in SRAM: CiM-SRAM;2021 IEEE 18th India Council International Conference (INDICON);2021-12-19
2. Approximate Memory: Data Storage in the Context of Approximate Computing;Information Storage;2019-11-20
3. A Reconfigurable Replica Bitline to Determine Optimum SRAM Sense Amplifier Set Time;Proceedings of the on Great Lakes Symposium on VLSI 2017;2017-05-10
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