Mathematical formalisms for performance evaluation of networks-on-chip

Author:

Kiasari Abbas Eslami1,Jantsch Axel1,Lu Zhonghai1

Affiliation:

1. KTH Royal Institute of Technology

Abstract

This article reviews four popular mathematical formalisms— queueing theory, network calculus, schedulability analysis , and dataflow analysis —and how they have been applied to the analysis of on-chip communication performance in Systems-on-Chip. The article discusses the basic concepts and results of each formalism and provides examples of how they have been used in Networks-on-Chip (NoCs) performance analysis. Also, the respective strengths and weaknesses of each technique and its suitability for a specific purpose are investigated. An open research issue is a unified analytical model for a comprehensive performance evaluation of NoCs. To this end, this article reviews the attempts that have been made to bridge these formalisms.

Funder

Intel Corporation

Publisher

Association for Computing Machinery (ACM)

Subject

General Computer Science,Theoretical Computer Science

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1. Machine learning-driven performance assessment of network-on-chip architectures;The Journal of Supercomputing;2024-07-11

2. Performance survey of classic and Optic network‐on‐chip;IET Circuits, Devices & Systems;2021-03-02

3. Bounding the delays of the MPPA network-on-chip with network calculus: Models and benchmarks;Performance Evaluation;2020-11

4. A Survey of Timing Verification Techniques for Multi-Core Real-Time Systems;ACM Computing Surveys;2020-05-31

5. Providing Integrity in Real-Time Networks-on-Chip;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2019-08

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