A log buffer-based flash translation layer using fully-associative sector translation

Author:

Lee Sang-Won1,Park Dong-Joo2,Chung Tae-Sun3,Lee Dong-Ho4,Park Sangwon5,Song Ha-Joo6

Affiliation:

1. Sungkyunkwan University, Suwon, Korea

2. Soongsil University, Seoul, Korea

3. Ajou University, Suwon, Korea

4. Hanyang University, Ansan, Korea

5. Hankook University of Foreign Studies, Yongin, Korea

6. Pukyong National University, Busan, Korea

Abstract

Flash memory is being rapidly deployed as data storage for mobile devices such as PDAs, MP3 players, mobile phones, and digital cameras, mainly because of its low electronic power, nonvolatile storage, high performance, physical stability, and portability. One disadvantage of flash memory is that prewritten data cannot be dynamically overwritten. Before overwriting prewritten data, a time-consuming erase operation on the used blocks must precede, which significantly degrades the overall write performance of flash memory. In order to solve this “erase-before-write” problem, the flash memory controller can be integrated with a software module, called “flash translation layer (FTL).” Among many FTL schemes available, the log block buffer scheme is considered to be optimum. With this scheme, a small number of log blocks, a kind of write buffer, can improve the performance of write operations by reducing the number of erase operations. However, this scheme can suffer from low space utilization of log blocks. In this paper, we show that there is much room for performance improvement in the log buffer block scheme, and propose an enhanced log block buffer scheme, called FAST (full associative sector translation). Our FAST scheme improves the space utilization of log blocks using fully-associative sector translations for the log block sectors. We also show empirically that our FAST scheme outperforms the pure log block buffer scheme.

Publisher

Association for Computing Machinery (ACM)

Subject

Hardware and Architecture,Software

Reference12 articles.

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2. System Software for Flash Memory: A Survey

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4. Algorithms and data structures for flash memories

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