A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance
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ACM Press
Cited by 53 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. RF Waveguide Pattern Engineering to Mitigate Bonding Surface Nonuniformities in CMOS Compatible Fabrication Processes;IEEE Transactions on Components, Packaging and Manufacturing Technology;2022-11
2. Process Variability Analysis in Interconnect, Logic, and Arithmetic Blocks of 16-nm FinFET FPGAs;ACM Transactions on Reconfigurable Technology and Systems;2021-09-30
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4. Variation-Aware Delay Fault Testing for Carbon-Nanotube FET Circuits;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2021-02
5. Testing Clock Distribution Networks;2017 IEEE 26th Asian Test Symposium (ATS);2017-11
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