Affiliation:
1. Georgia Institute of Technology, Atlanta, GA
2. Sandia National Laboratories, Albuquerque, NM
Abstract
Dennard scaling has ended. Lowering the voltage supply (
V
dd
) to sub-volt levels causes intermittent losses in signal integrity, rendering further scaling (down) no longer acceptable as a means to lower the power required by a processor core. However, it is possible to correct the occasional errors caused due to lower
V
dd
in an efficient manner and effectively lower power. By deploying the right amount and kind of redundancy, we can strike a balance between overhead incurred in achieving reliability and energy savings realized by permitting lower
V
dd
. One promising approach is the Redundant Residue Number System (RRNS) representation. Unlike other error correcting codes, RRNS has the important property of being closed under addition, subtraction and multiplication, thus enabling computational error correction at a fraction of an overhead compared to conventional approaches. We use the RRNS scheme to design a Computationally-Redundant, Energy-Efficient core, including the microarchitecture, Instruction Set Architecture (ISA) and RRNS centered algorithms. From the simulation results, this RRNS system can reduce the energy-delay-product by about 3× for multiplication intensive workloads and by about 2× in general, when compared to a non-error-correcting binary core.
Funder
Laboratory-Directed Research and Development (LDRD) Project
National Technology and Engineering Solutions of Sandia, LLC.
Honeywell International, Inc.
U.S. Department of Energy's National Nuclear Security Administration
Publisher
Association for Computing Machinery (ACM)
Subject
Hardware and Architecture,Information Systems,Software
Reference94 articles.
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