The SuperCodelet architecture-Reference-Cited by-同舟云学术

The SuperCodelet architecture

Published:2022-04-02 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 1st International Workshop on Extreme Heterogeneity Solutions
language:
Short-container-title:

Author:

Diaz Jose M Monsalve¹,Harms Kevin¹,Guaitero Rafael A. Herrera²,Perdomo Diego A. Roa²,Kumaran Kalyan¹,Gao Guang R.

Affiliation:

1. Argonne National Lab

2. University of Delaware

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3529336.3530823

Reference20 articles.

1. Architecture of the IBM System/360

2. Andrew S. Cassidy , Jun Sawada , Paul Merolla , John V. Arthur , Rodrigo Alvarez-Icaza , Filipp Akopyan , Bryan L. Jackson , and Dharmendra S . Modha . 2016 . TrueNorth: A High-Performance, Low-Power Neurosynaptic Processor for Multi-Sensory Perception, Action, and Cognition . Andrew S. Cassidy, Jun Sawada, Paul Merolla, John V. Arthur, Rodrigo Alvarez-Icaza, Filipp Akopyan, Bryan L. Jackson, and Dharmendra S. Modha. 2016. TrueNorth: A High-Performance, Low-Power Neurosynaptic Processor for Multi-Sensory Perception, Action, and Cognition.

3. E. Castillo , L. Alvarez , M. Moreto , M. Casas , E. Vallejo , J. L. Bosque , R. Beivide , and M. Valero . 2018 . Architectural Support for Task Dependence Management with Flexible Software Scheduling. In 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA). 283--295 . E. Castillo, L. Alvarez, M. Moreto, M. Casas, E. Vallejo, J. L. Bosque, R. Beivide, and M. Valero. 2018. Architectural Support for Task Dependence Management with Flexible Software Scheduling. In 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA). 283--295.

4. Task Superscalar: An Out-of-Order Task Pipeline

5. G. Gupta and G. S. Sohi . 2011. Dataflow execution of sequential imperative programs on multicore architectures . In 2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). 59--70 . G. Gupta and G. S. Sohi. 2011. Dataflow execution of sequential imperative programs on multicore architectures. In 2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). 59--70.

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Towards Fault Tolerance and Resilience in the Sequential Codelet Model;Communications in Computer and Information Science;2024

2. Enabling HW-Based Task Scheduling in Large Multicore Architectures;IEEE Transactions on Computers;2024-01

3. A gem5 Implementation of the Sequential Codelet Model: Reducing Overhead and Expanding the Software Memory Interface;Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, Network, Storage, and Analysis;2023-11-12

4. Towards Maximum Throughput of Dataflow Software Pipeline under Resource Constraints;Proceedings of the 14th International Workshop on Programming Models and Applications for Multicores and Manycores;2023-02-25