A core calculus for secure hardware
Author:
Affiliation:
1. University of Missouri
2. US Naval Research Laboratory
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/3127041.3127048
Reference40 articles.
1. A. Azevedo de Amorim N. Collins A. DeHon D. Demange C. Hriţcu D. Pichardie B. Pierce R. Pollack and A. Tolmach. 2014. A Verified Information-flow Architecture. In POPL. 165--178. 10.1145/2535838.2535839 A. Azevedo de Amorim N. Collins A. DeHon D. Demange C. Hriţcu D. Pichardie B. Pierce R. Pollack and A. Tolmach. 2014. A Verified Information-flow Architecture. In POPL. 165--178. 10.1145/2535838.2535839
2. Thomas Braibant and Adam Chlipala. 2013. Formal Verification of Hardware Synthesis. In CAV. 213--228. Thomas Braibant and Adam Chlipala. 2013. Formal Verification of Hardware Synthesis. In CAV . 213--228.
3. BDD-Based Hardware Verification
4. D. Cock G. Klein and T. Sewell. 2008. Secure Microkernels State Monads and Scalable Refinement. In TPHOLs. 167--182. 10.1007/978-3-540-71067-7_16 D. Cock G. Klein and T. Sewell. 2008. Secure Microkernels State Monads and Scalable Refinement. In TPHOLs. 167--182. 10.1007/978-3-540-71067-7_16
5. A monadic analysis of information flow security with mutable state
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