Migration-aware WCET estimation for heterogeneous multi-cores

Abstract

Heterogeneous Multi-Processor Systems-on-Chip (MPSoCs) are increasingly used in the embedded safety-critical domain with real-time constraints. Fault tolerance, temperature distribution, and energy management in such systems can be improved by reconfiguration mechanisms that rely on task migration. In order to serve a migration request while meeting all deadlines, the remaining worst-case execution time (WCET) must be known as tightly bound as possible. We show that scaling the WCET by a linear factor to compensate for migration between heterogeneous cores can lead to dangerous underestimations. Our approach is to split the WCET of a task into parts and derive the WCET for all parts on all individual core architectures. We present a formal model to show how the remaining WCET can be calculated as the sum of unprocessed parts. We differentiate between two levels of heterogeneity, namely same instruction set architecture (ISA) with different performance characteristics and different ISAs. We propose three implementation concepts to partition a task, calculate the remaining WCET, and perform the migration.