Affiliation:
1. University of Zaragoza
2. UPC Barcelona Tech
Abstract
Hardware data prefetch is a very well known technique for hiding memory latencies. However, in a multicore system fitted with a shared Last-Level Cache (LLC), prefetch induced by a core consumes common resources such as shared cache space and main memory bandwidth. This may degrade the performance of other cores and even the overall system performance unless the prefetch aggressiveness of each core is controlled from a system standpoint. On the other hand, LLCs in commercial chip multiprocessors are more and more frequently organized in independent banks. In this contribution, we target for the first time prefetch in a banked LLC organization and propose ABS, a low-cost controller with a hill-climbing approach that runs stand-alone at each LLC bank without requiring inter-bank communication. Using multiprogrammed SPEC2K6 workloads, our analysis shows that the mechanism improves both user-oriented metrics (Harmonic Mean of Speedups by 27% and Fairness by 11%) and system-oriented metrics (Weighted Speedup increases 22% and Memory Bandwidth Consumption decreases 14%) over an eight-core baseline system that uses aggressive sequential prefetch with a fixed degree. Similar conclusions can be drawn by varying the number of cores or the LLC size, when running parallel applications, or when other prefetch engines are controlled.
Funder
Spanish Government and European ERDF
Publisher
Association for Computing Machinery (ACM)
Subject
Hardware and Architecture,Information Systems,Software
Cited by
8 articles.
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1. Berti: an Accurate Local-Delta Data Prefetcher;2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO);2022-10
2. Combining Prefetch Control and Cache Partitioning to Improve Multicore Performance;2019 IEEE International Parallel and Distributed Processing Symposium (IPDPS);2019-05
3. A Survey of Recent Prefetching Techniques for Processor Caches;ACM Computing Surveys;2017-06-30
4. Band-Pass Prefetching;ACM Transactions on Architecture and Code Optimization;2017-06-30
5. SPAC:A Synergistic Prefetcher Aggressiveness Controller for Multi-core Systems;IEEE Transactions on Computers;2016