A Survey of Recent Prefetching Techniques for Processor Caches

Author:

Mittal Sparsh1ORCID

Affiliation:

1. Oak Ridge National Laboratory, Tennessee

Abstract

As the trends of process scaling make memory systems an even more crucial bottleneck, the importance of latency hiding techniques such as prefetching grows further. However, naively using prefetching can harm performance and energy efficiency and, hence, several factors and parameters need to be taken into account to fully realize its potential. In this article, we survey several recent techniques that aim to improve the implementation and effectiveness of prefetching. We characterize the techniques on several parameters to highlight their similarities and differences. The aim of this survey is to provide insights to researchers into working of prefetching techniques and spark interesting future work for improving the performance advantages of prefetching even further.

Funder

Advanced Scientific Computing Research

U.S. Department of Energy

Office of Science

Publisher

Association for Computing Machinery (ACM)

Subject

General Computer Science,Theoretical Computer Science

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2. Triangel: A High-Performance, Accurate, Timely On-Chip Temporal Prefetcher;2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA);2024-06-29

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