Affiliation:
1. Electrical Engineering - Israel Institute of Technology
2. Electrical Engineering and Computer Science Technion - Israel Institute of Technology
Abstract
We present the single-graph multiple-flows (SGMF) architecture that combines coarse-grain reconfigurable computing with dynamic dataflow to deliver massive thread-level parallelism. The CUDA-compatible SGMF architecture is positioned as an energy efficient design alternative for GPGPUs.
The architecture maps a compute kernel, represented as a dataflow graph, onto a coarse-grain reconfigurable fabric composed of a grid of interconnected functional units. Each unit dynamically schedules instances of the same static instruction originating from different CUDA threads. The dynamically scheduled functional units enable streaming the data of multiple threads (or graph flows, in SGMF parlance) through the grid. The combination of statically mapped instructions and direct communication between functional units obviate the need for a full instruction pipeline and a centralized register file, whose energy overheads burden GPGPU
We show that the SGMF architecture delivers performance comparable to that of contemporary GPGPUs while consuming 57% less energy on average.
Funder
Seventh Framework Programme
Israel Science Foundation
Publisher
Association for Computing Machinery (ACM)
Cited by
24 articles.
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