Architecting a hardware-managed hybrid DIMM optimized for cost/performance

Author:

Ware Fred1,Bueno Javier2,Gopalakrishnan Liji1,Haukness Brent1,Haywood Chris1,Juan Toni2,Linstadt Eric1,McKee Sally A.3,Woo Steven C.1,Wright Kenneth L.1,Hampel Craig1,Bronner Gary1

Affiliation:

1. Rambus Inc.

2. Metempsy, Barcelona, Spain

3. Clemson University

Publisher

ACM

Reference41 articles.

1. 256 Gb 3 b/Cell V-nand Flash Memory With 48 Stacked WL Layers

2. B. Tallis "Samsung at Flash Memory Summit: 96-Layer V-NAND MLC Z-NAND New Interfaces " AnandTech 9 August 2017. B. Tallis "Samsung at Flash Memory Summit: 96-Layer V-NAND MLC Z-NAND New Interfaces " AnandTech 9 August 2017.

3. J. Choe "SK hynix' 21 nm DRAM Cell Technology: Comparison of 1st and 2nd generation " Tech Insights 5 June 2017. {Online}. Available: http://techinsights.com/about-techinsights/overview/blog/sk-hynix-21-nm-dram-cell-technology-comparison-of-1st-and-2nd-generation/. {Accessed 12 November 2017}. J. Choe "SK hynix' 21 nm DRAM Cell Technology: Comparison of 1st and 2nd generation " Tech Insights 5 June 2017. {Online}. Available: http://techinsights.com/about-techinsights/overview/blog/sk-hynix-21-nm-dram-cell-technology-comparison-of-1st-and-2nd-generation/. {Accessed 12 November 2017}.

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