Isadora

Author:

Deutschbein Calvin1,Meza Andres2,Restuccia Francesco3,Kastner Ryan2,Sturton Cynthia1

Affiliation:

1. University of North Carolina at Chapel Hill, Chapel Hill, NC, USA

2. University of California, San Diego, San Diego, CA, USA

3. Scuola Superiore Santa-Anna Pisa, Pisa, Italy

Funder

NSF

Intel Corporation

NSF (National Science Foundation)

Semiconductor Research Corporation

Publisher

ACM

Reference45 articles.

1. [n.d.]. The Common Weakness Enumeration Official Webpage. https://cwe.mitre.org/ [n.d.]. The Common Weakness Enumeration Official Webpage. https://cwe.mitre.org/

2. [n.d.]. Questa Advanced Simulator. https://eda.sw.siemens.com/en-US/ic/questa/simulation/advanced-simulator/ [n.d.]. Questa Advanced Simulator. https://eda.sw.siemens.com/en-US/ic/questa/simulation/advanced-simulator/

3. [n.d.]. Radix Coverage for Hardware Common Weakness Enumeration (CWE) Guide. https://tortugalogic.com/wp-content/uploads/2020/03/RadixCWEGuide_20210126.pdf. [n.d.]. Radix Coverage for Hardware Common Weakness Enumeration (CWE) Guide. https://tortugalogic.com/wp-content/uploads/2020/03/RadixCWEGuide_20210126.pdf.

4. Clepsydra: Modeling timing flows in hardware designs

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1. Towards Zero-Trust Hardware Architectures in Safety and Security Critical System-on-Chips;2024 IEEE 3rd Real-Time and Intelligent Edge Computing Workshop (RAGE);2024-05-13

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4. Secure Instruction and Data-Level Information Flow Tracking Model for RISC-V;Cryptography;2023-11-16

5. SEIF: Augmented Symbolic Execution for Information Flow in Hardware Designs;Proceedings of the 12th International Workshop on Hardware and Architectural Support for Security and Privacy;2023-10-29

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