Hardware read-write lock elision
Author:
Affiliation:
1. University of Neuchâtel
2. University of Lisbon
3. MIT
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/2901318.2901346
Reference33 articles.
1. Transactional programming in a multi-core environment
2. Software-improved hardware lock elision
3. Pessimistic Software Lock-Elision
4. Robust architectural support for transactional memory in the power architecture
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