Memory and Energy Efficient Memory Model and Instruction Set Architectures for Tree Data Structures

Author:

Rifai Mouad1,Johnsson Lennart1

Affiliation:

1. University of Houston, United States

Funder

University of Houston

Publisher

ACM

Reference42 articles.

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2. Tutu Ajayi , Khalid Al-Hawaj , Aporva Amarnath , Steve Dai , Scott Davidson , Paul Gao , Gai Liu , Atieh Lotfi , Julian Puscar , Anuj Rao , 2017 . Celerity: An open source RISC-V tiered accelerator fabric . In Hot Chips: A Symposium on High Performance Chips. Tutu Ajayi, Khalid Al-Hawaj, Aporva Amarnath, Steve Dai, Scott Davidson, Paul Gao, Gai Liu, Atieh Lotfi, Julian Puscar, Anuj Rao, 2017. Celerity: An open source RISC-V tiered accelerator fabric. In Hot Chips: A Symposium on High Performance Chips.

3. In-Memory Low-Cost Bit-Serial Addition Using Commodity DRAM Technology

4. D. Aspinall , W.A. Clark , W.A. Clark , D. Aspinall , and I.M. Barron . 1978 . The Microprocessor and its Application: An Advanced Course . Cambridge University Press . 47–50 pages. D. Aspinall, W.A. Clark, W.A. Clark, D. Aspinall, and I.M. Barron. 1978. The Microprocessor and its Application: An Advanced Course. Cambridge University Press. 47–50 pages.

5. Daniel E. Atkins III. 1967. The theory and implementation of SRT Division. Report No. 230. Master's thesis. Univ. of Illinois at Urbana-Champaign. https://doi.org/10.2172/4561774 10.2172/4561774

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