Affiliation:
1. Department of Computer Science, University of North Carolina, Chapel Hill, NC
2. Department of Mathematics, Carleton College, Northfield, MN.
Abstract
This paper introduces the architecture and initial algorithms for Pixel-Planes 5, a heterogeneous multi-computer designed both for high-speed polygon and sphere rendering (1M Phong-shaded triangles/second) and for supporting algorithm and application research in interactive 3D graphics. Techniques are described for volume rendering at multiple frames per second, font generation directly from conic spline descriptions, and rapid calculation of radiosity form-factors. The hardware consists of up to 32 math-oriented processors, up to 16 rendering units, and a conventional 1280 × 1024-pixel frame buffer, interconnected by a 5 gigabit ring network. Each rendering unit consists of a 128 × 128-pixel array of processors-with-memory with parallel quadratic expression evaluation for every pixel. Implemented on 1.6 micron CMOS chips designed to run at 40MHz, this array has 208 bits/pixel on-chip and is connected to a video RAM memory system that provides 4,096 bits of off-chip memory. Rendering units can be independently reasigned to any part of the screen or to non-screen-oriented computation. As of April 1989, both hardware and software are still under construction, with initial system operation scheduled for fall 1989.
Publisher
Association for Computing Machinery (ACM)
Subject
Computer Graphics and Computer-Aided Design,General Computer Science
Cited by
106 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Boustrophedonic Frames: Quasi-Optimal L2 Caching for Textures in GPUs;2023 32nd International Conference on Parallel Architectures and Compilation Techniques (PACT);2023-10-21
2. DTexL: Decoupled Raster Pipeline for Texture Locality;2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO);2022-10
3. SPIDER: An Effective, Efficient and Robust Load Scheduler for Real-time Split Frame Rendering;2022 IEEE International Parallel and Distributed Processing Symposium (IPDPS);2022-05
4. TCOR: A Tile Cache with Optimal Replacement;2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA);2022-04
5. Mach-RT: A Many Chip Architecture for High Performance Ray Tracing;IEEE Transactions on Visualization and Computer Graphics;2022-03-01