COALA-Reference-Cited by-同舟云学术

COALA

Published:2020-11-02 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 39th International Conference on Computer-Aided Design
language:
Short-container-title:

Author:

Jiang Yun-Jhe¹,Fang Shao-Yun¹

Affiliation:

1. National Taiwan University of Science and Technology, Taipei, Taiwan

Funder

Ministry of Science and Technology

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3400302.3415721

Reference19 articles.

1. NCTU-GR: Efficient Simulated Evolution-Based Rerouting and Congestion-Relaxed Layer Assignment on 3-D Global Routing

2. C.-H. Hsu H.-Y. Chen and Y.-W. Chang "Multilayer Global Routing With Via and Wire Capacity Considerations " in Transactions on Computer-Aided Design of Integrated Circuits and Systems 2010. C.-H. Hsu H.-Y. Chen and Y.-W. Chang "Multilayer Global Routing With Via and Wire Capacity Considerations " in Transactions on Computer-Aided Design of Integrated Circuits and Systems 2010.

3. T.-H. Lee and T.-C. Wang "Congestion-Constrained Layer Assignment for Via Minimization in Global Routing " in Transactions on Computer-Aided Design of Integrated Circuits and Systems 2008. T.-H. Lee and T.-C. Wang "Congestion-Constrained Layer Assignment for Via Minimization in Global Routing " in Transactions on Computer-Aided Design of Integrated Circuits and Systems 2008.

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1. A Novel Global Routing Algorithm for Printed Circuit Boards Based on Triangular Grid;Electronics;2023-12-08

2. A Global Routing Algorithm for PCB Based on Triangular Grid;2023 5th International Conference on Circuits and Systems (ICCS);2023-10-27

3. Airgap Insertion and Layer Reassignment Under Setup and Hold Timing Constraints;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-03

4. LA-SVR: A High-Performance Layer Assignment Algorithm with Slew Violations Reduction;2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC);2022-10-03

5. Timing-Aware Layer Assignment for Advanced Process Technologies Considering Via Pillars;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2021