Timing-Aware Layer Assignment for Advanced Process Technologies Considering Via Pillars-Reference-Cited by-同舟云学术

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Timing-Aware Layer Assignment for Advanced Process Technologies Considering Via Pillars

Published:2021 Issue: Volume: Page:1-1
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Liu Genggeng,Zhang Xinghai,Guo Wenzhong,Huang Xing,Liu Wen-Hao,Chao Kai-Yuan,Wang Ting-Chi

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx7/43/6917053/09496599.pdf?arnumber=9496599

Cited by 37 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Multi-Strategy Bus Deviation-Driven Layer Assignment Algorithm;2024 2nd International Symposium of Electronics Design Automation (ISEDA);2024-05-10

2. Timing-Driven Obstacle-Avoiding X-Architecture Steiner Minimum Tree Algorithm With Slack Constraints;IEEE Transactions on Systems, Man, and Cybernetics: Systems;2024-05

3. Design and Implementation of Virtual Reality Experiment Project of Integrated Circuit Routing Algorithm;Communications in Computer and Information Science;2024

4. LIVER DETECTION ALGORITHM BASED ON LOCAL INFORMATION FUSION;Journal of Mechanics in Medicine and Biology;2023-07-22

5. A Novel Joint Frequency Offset Estimation Scheme for OFDM System;J INF SCI ENG;2023

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