A customized graph neural network model for guiding analog IC placement
Author:
Affiliation:
1. Texas A&M University
2. University of Minnesota
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/3400302.3415624
Reference25 articles.
1. Automatic generation of parasitic constraints for performance-constrained physical design of analog circuits
2. A performance-driven placement tool for analog integrated circuits
3. Symmetry within the sequence-pair representation in the context of placement for analog design;Balasa F.;IEEE TCAD,2000
4. Analog placement based on symmetry-island formulation;Lin P.-H.;IEEE TCAD,2009
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