Timing errors in LDPC decoding computations with overscaled supply voltage
Author:
Affiliation:
1. University of Notre Dame, Notre Dame, IN, USA
2. Bell Labs, Alcatel-Lucent, Murray Hill, NJ, USA
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/2627369.2627638
Reference20 articles.
1. Computation Error Analysis in Digital Signal Processing Systems With Overscaled Supply Voltage
2. Design of Low-Voltage Digital Building Blocks and ADCs for Energy-Efficient Systems
3. A Near-Optimum Dynamic Voltage Scaling (DVS) in 65-nm Energy-Efficient Power Management With Frequency-Based Control (FBC) for SoC System
4. Process-Variation Resilient and Voltage-Scalable DCT Architecture for Robust Low-Power Computing
5. A Self-Tuning DVS Processor Using Delay-Error Detection and Correction
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1. Low Power LDPC Decoding by Reliable Voltage Down-Scaling;2023 IEEE Nordic Circuits and Systems Conference (NorCAS);2023-10-31
2. Bridging the Gap Between Voltage Over-Scaling and Joint Hardware Accelerator-Algorithm Closed-Loop;IEEE Transactions on Circuits and Systems for Video Technology;2022-01
3. On the Resiliency of NCFET Circuits Against Voltage Over-Scaling;IEEE Transactions on Circuits and Systems I: Regular Papers;2021-04
4. Modeling and Energy Optimization of LDPC Decoder Circuits With Timing Violations;IEEE Transactions on Communications;2018-03
5. Stochastic Computing Improves the Timing-Error Tolerance and Latency of Turbo Decoders: Design Guidelines and Tradeoffs;IEEE Access;2016
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