Technology/Memory Co-Design and Co-Optimization Using E-Tree Interconnect-Reference-Cited by-同舟云学术

Technology/Memory Co-Design and Co-Optimization Using E-Tree Interconnect

Published:2023-06-05 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the Great Lakes Symposium on VLSI 2023
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Author:

Pei Zhenlin¹^ORCID,Mayahinia Mahta²^ORCID,Liu Hsiao-Hsuan³^ORCID,Tahoori Mehdi²^ORCID,Catthoor Francky³^ORCID,Tokei Zsolt⁴^ORCID,Pan Chenyun¹^ORCID

Affiliation:

1. The University of Texas at Arlington, Arlington, TX, USA

2. Karlsruhe Institute of Technology (KIT), Karlsruhe, Germany

3. IMEC and Katholieke Universiteit Leuven (KU Leuven), Leuven, Belgium

4. IMEC, Leuven, Belgium

Funder

National Science Foundation

Department of Energy

IMEC

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3583781.3590311

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4. G. Bonilla , N. Lanzillo , C.-K. Hu , C. Penny , and A. Kumar , " Interconnect scaling challenges, and opportunities to enable system-level performance beyond 30 nm pitch," in 2020 IEEE International Electron Devices Meeting (IEDM) , 2020 , pp. 20.4 . 1--20.4. 4: IEEE. G. Bonilla, N. Lanzillo, C.-K. Hu, C. Penny, and A. Kumar, "Interconnect scaling challenges, and opportunities to enable system-level performance beyond 30 nm pitch," in 2020 IEEE International Electron Devices Meeting (IEDM), 2020, pp. 20.4. 1--20.4. 4: IEEE.

5. Adapting Interconnect Technology to Multigate Transistors for Optimum Performance

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1. CFET SRAM With Double-Sided Interconnect Design and DTCO Benchmark;IEEE Transactions on Electron Devices;2023-10