Design of Quantum Dot Cellular Automata Based Parity Generator and Checker with Minimum Clocks and Latency
Author:
Publisher
MECS Publisher
Subject
Computer Science Applications,Education
Link
http://www.mecs-press.org/ijmecs/ijmecs-v8-n8/IJMECS-V8-N8-2.pdf
Cited by 14 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Optimizing fault tolerance of RAM cell through MUX based modeling and design using symmetries of QCA cells;Scientific Reports;2024-04-13
2. Optimizing Fault Tolerance of RAM cell through MUX based Modeling and Design using symmetries of QCA Cells;2024-01-15
3. Cost Efficient Design Of Error Detection Circuit For Nano Communication;2022 International Conference on Computing, Communication and Power Technology (IC3P);2022-01
4. Quantum dot Cellular Automata based Fault Tolerant Fingerprint Authentication Systems using Reversible Logic Gates;GAZI UNIVERSITY JOURNAL OF SCIENCE;2021-04-15
5. Design and execution of programmable logic device using quantum dot cellular automata;Materials Today: Proceedings;2021-03
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