Co-optimization of memory BIST grouping, test scheduling, and logic placement-Reference-Cited by-同舟云学术

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Co-optimization of memory BIST grouping, test scheduling, and logic placement

Published:2014 Issue: Volume: Page:
ISSN:
Container-title:Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014
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Author:

Kahng Andrew B.,Kang Ilgweon

Publisher

IEEE Conference Publications

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. An Efficient Grouping Algorithm with Build-in-Self-Test for Multiple Memories;2024 2nd International Symposium of Electronics Design Automation (ISEDA);2024-05-10

2. An Efficient Grouping Method for Large-Scale MBIST;2024 2nd International Symposium of Electronics Design Automation (ISEDA);2024-05-10

3. Built-In Self-Test Architecture Enabling Diagnosis for Massive Embedded Memory Banks in Large SoCs;Electronics;2024-01-10

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