Built-In Self-Test Architecture Enabling Diagnosis for Massive Embedded Memory Banks in Large SoCs-Reference-Cited by-同舟云学术

Built-In Self-Test Architecture Enabling Diagnosis for Massive Embedded Memory Banks in Large SoCs

Published:2024-01-10 Issue:2 Volume:13 Page:303
ISSN:2079-9292
Container-title:Electronics
language:en
Short-container-title:Electronics

Author:

Bernardi Paolo¹^ORCID,Guerriero Augusto Maria¹,Insinga Giorgio¹^ORCID,Paganini Giovanni¹,Carnevale Giambattista²,Coppetta Matteo²,Mischo Walter³,Ullmann Rudolf³

Affiliation:

1. Diparimento di Automatica e Informatica (DAUIN), Politecnico di Torino, 10129 Torino, Italy

2. Infineon Technologies, 35131 Padova, Italy

3. Infineon Technologies, 85579 Neubiberg, Germany

Abstract

This paper describes a hardware/software strategy for the effective and efficient management of several distributed Memory Built-In Self-Test (MBIST) units orchestrated by a single CPU to enable the parallel testing of several memory banks. Experimental testing of the implementation on an Infineon chip shows up to a 25% test time reduction compared to traditional strategies, especially in cases for which there are a large number of failures affecting several banks. Additionally, it permits balanced failure collection from different banks in cases for which there are limitations to the storage of failure-related information.

Publisher

MDPI AG

Subject

Electrical and Electronic Engineering,Computer Networks and Communications,Hardware and Architecture,Signal Processing,Control and Systems Engineering

Link

https://www.mdpi.com/2079-9292/13/2/303/pdf

Reference17 articles.

1. Van De Goor, A., Gaydadjiev, G., and Hamdioui, S. (2010, January 8–12). Memory testing with a RISC microcontroller. Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), Dresden, Germany.

2. Saliency-Based Defect Detection in Industrial Images by Using Phase Spectrum;Bai;IEEE Trans. Ind. Inform.,2014

3. Yeh, J.C., Kuo, S.F., Wu, C.W., Huang, C.T., and Chen, C.H. (2005, January 3–5). A systematic approach to reducing semiconductor memory test time in mass production. Proceedings of the 2005 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT’05), Taipei, Taiwan.

4. Singh, A., Kumar, G.M., and Aasti, A. (2020, January 22–23). Controller Architecture for Memory BIST Algorithms. Proceedings of the IEEE International Students’ Conference on Electrical, ELectronics and Computer Science (SCEECS), Bhopal, India.

5. Chen, J.T., Khare, J., Walker, K., Shaikh, S., Rajski, J., and Maly, W. (2001, January 1). Test response compression and bitmap encoding for embedded memories in manufacturing process monitoring. Proceedings of the International Test Conference, Baltimore, MD, USA.