Built-In Self-Test Architecture Enabling Diagnosis for Massive Embedded Memory Banks in Large SoCs
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Published:2024-01-10
Issue:2
Volume:13
Page:303
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ISSN:2079-9292
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Container-title:Electronics
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language:en
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Short-container-title:Electronics
Author:
Bernardi Paolo1ORCID, Guerriero Augusto Maria1, Insinga Giorgio1ORCID, Paganini Giovanni1, Carnevale Giambattista2, Coppetta Matteo2, Mischo Walter3, Ullmann Rudolf3
Affiliation:
1. Diparimento di Automatica e Informatica (DAUIN), Politecnico di Torino, 10129 Torino, Italy 2. Infineon Technologies, 35131 Padova, Italy 3. Infineon Technologies, 85579 Neubiberg, Germany
Abstract
This paper describes a hardware/software strategy for the effective and efficient management of several distributed Memory Built-In Self-Test (MBIST) units orchestrated by a single CPU to enable the parallel testing of several memory banks. Experimental testing of the implementation on an Infineon chip shows up to a 25% test time reduction compared to traditional strategies, especially in cases for which there are a large number of failures affecting several banks. Additionally, it permits balanced failure collection from different banks in cases for which there are limitations to the storage of failure-related information.
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