A low-power, high-performance approximate multiplier with configurable partial error recovery

Author:

Liu Cong,Han Jie,Lombardi Fabrizio

Publisher

IEEE Conference Publications

Cited by 18 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Design and FPGA implementation of recursive multiplier using approximated 4:2 compressor;AIP Conference Proceedings;2024

2. Power–Area-Optimized Approximate Multiplier Design for Image Fusion;Circuits, Systems, and Signal Processing;2023-12-19

3. Evaluating Sign Error Correction for Approximate Adders Employing ECG Signal Processing;2023 10th International Conference on Electrical Engineering, Computer Science and Informatics (EECSI);2023-09-20

4. Design and Performance Analysis of RNS-Based Reconfigurable FIR Filter for Noise Removal in Speech Signals Applications;WSEAS TRANSACTIONS ON SYSTEMS AND CONTROL;2023-06-16

5. An Accuracy Reconfigurable Vector Accelerator based on Approximate Logarithmic Multipliers for Energy-Efficient Computing;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2023-03-01

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