1. Soft and Hard Error-Correction Techniques in STT-MRAM;IEEE Design & Test;2024-10
2. Silent Data Corruption and Reliability Risks due to Faults Affecting High Performance Microprocessors’ Caches*;2024 IEEE 30th International Symposium on On-Line Testing and Robust System Design (IOLTS);2024-07-03
3. Hybrid Hardware/Software Detection of Multi-Bit Upsets in Memory;2024 54th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W);2024-06-24
4. Investigating Memory Failure Prediction Across CPU Architectures;2024 54th Annual IEEE/IFIP International Conference on Dependable Systems and Networks - Supplemental Volume (DSN-S);2024-06-24
5. LWECC: A Lightweight ECC Technology for HPC Accelerators Supporting Multi-granularity Memory Access;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19