Wafer Dicing Using Dry Etching on Standard Tapes and Frames

Author:

Lishan David1,Lazerand Thierry1,Mackenzie Kenneth1,Pays-Volard David1,Martinez Linnell1,Grivna Gordy2,Doub Jason2,Tessier Ted3,Burgess Guy3

Affiliation:

1. 1Plasma-Therm LLC, 10050 16th St. North, St. Petersburg, FL 33716 USA

2. 2ON Semiconductor, 5005 E. McDowell Road, Phoenix, AZ 85008 USA

3. 3FlipChip International, 3701 E. University Drive, Phoenix, AZ 85034 USA

Abstract

To meet the changing demands of consumer product form factors, there has been a steady shift to thinner and smaller semiconductor die, both of which increase the challenges for die singulation. The traditional approach of saw dicing is facing new limitations due to die damage and throughput. Compounding these issues is the finite width of saw blades, saw blade loading from clearing multiple materials, and orthogonal layout restrictions. Laser dicing has been introduced to address some of these issues, but faces other limitations such as damage from the heat affected zone, ablation residues, throughput, and material incompatibilities (changes in transparency and absorption in the street). In some cases, a combination of both saw and laser has been utilized to surmount some of the technical obstacles. The recently introduced approach of front-side plasma singulation circumvents many of the limitations of saws and lasers. The technology presented in this work uses standard dicing tape and frames, is through-wafer complete die separation, and does not involve a subsequent wafer thinning or die cleaving step. Our approach utilizes lithographically defined singulation lines with typical widths of 10–15μm, and delivers chip/crack-free edges with low-stress rounded corners. The parallel nature of this singulation method enables non-orthogonal and non-linear singulation streets allowing die layout and design flexibility not achievable by saws and/or lasers. As a consequence, plasma singulation produces increased good die per wafer through better wafer area utilization, lower die failure (reduced corner stress with rounded geometry), and flexibility in die placement near wafer edge on larger die. One of the unique advantages is that this technology can be implemented without addition of any new masking layers but instead the use of the existing passivation, metals and/or upper dielectrics as masks. Implementing this technology across a wide range of die applications such as power, memory, logic, imaging sensors, LEDs, and MEMS must address a diverse range of variables such as compatible materials, bond pads/bumps, and backmetal. For dies with backside metal, a non-etch based method to allow full die separation while the dies are still attached to tape has been demonstrated.

Publisher

IMAPS - International Microelectronics Assembly and Packaging Society

Subject

General Medicine

Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Back Cavity Formation on 50µm Thick bumped PMUT wafers;2022 IEEE 24th Electronics Packaging Technology Conference (EPTC);2022-12-07

2. 300mm Full Thickness Si-Based IC Singulation Using Plasma Dicing for Advanced Packaging Technologies;2022 IEEE 72nd Electronic Components and Technology Conference (ECTC);2022-05

3. Pathfinding for 2.5D interconnect technologies;Proceedings of the Workshop on System-Level Interconnect: Problems and Pathfinding Workshop;2020-11-05

4. Fundamentals and Failures in Die Preparation for 3D Packaging;3D Microelectronic Packaging;2017

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