Chiplet Integration by Die-to-Die Pillar-Suspended Bridge

Abstract

Chiplet integration technology, which has the potential to scalable expand capabilities by integrating many integrated circuit (IC) chips with different manufacturing processes, structures, and functions while maintaining the data transfer bandwidth between IC chips, is attracting attention as a promising method to solve the problems such as slowdown of Moore’s law and the von Neumann bottleneck. Die-to-die bridge structures that connect dies via locally placed bridge chips with high-density interconnects is expected for scalable chiplet integration. We proposed novel die-to-die bridge architecture called “Pillar-Suspended Bridge (PSB)” that connects between chiplet and bridge via “MicroPillars” in molded form using panel-level manufacturing process. We successfully demonstrated proof-of-concept (PoC) through prototyping chiplets/bridge integrated module with 40 µm pitch MicroPillars using 300 mm × 300 mm panel-level manufacturing process. We confirmed fine-pitch die-to-die connection with MicroPillars and 20 µm thick bridge die by cross-sectional analysis of the module. We also evaluated warpage behavior of the PSB module in the reflow temperature range using shadow moiré method and confirmed warpage of less than 10 µm. Finally, we discussed scalability of this technology including external connections for Fan-Out RDL and optics.