Six-Side Molded Panel-Level Chip-Scale Package with Multiple Diced Wafers

Author:

Lau John H.,Ko Cheng-Ta,Tseng Tzvy-Jang,Peng Chia-Yu,Yang Kai-Ming,Xia Tim,Lin Puru Bruce,Lin Eagle,Chang Leo,Liu Hsing Ning,Lin Curry,Cheng David,Lu Winnie

Abstract

Abstract In this study, the design, materials, process, assembly, and reliability of a six-side molded panel-level chip-scale package (PLCSP) are presented. Emphasis is placed on the fabrication of the redistribution layers (RDLs) of the PLCSP on a large temporary panel with multiple device wafers. Because all the printed circuited board (PCB) panels are in rectangular shape, some of the device wafers are diced into two or more pieces so the panel is fully utilized. Thus, it is very high throughput. Because all the processes/equipment are PCB processes/equipment (not semiconductor process/equipment), it is a very low-cost process. After the fabrication of RDLs, the wafers from the PCB panel were debonded. It is followed by solder ball mounting and fabricating the six-side molded PLCSP from the original device wafers with RDLs. The drop test and the results including failure analysis of the PLCSP are presented. Thermal cycling of the six-side molded PLCSP PCB assembly is performed by a nonlinear temperature- and time-dependent finite-element simulation.

Publisher

IMAPS - International Microelectronics Assembly and Packaging Society

Subject

Electrical and Electronic Engineering,Computer Networks and Communications,Electronic, Optical and Magnetic Materials

Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. State-Of-The-Art of Advanced Packaging;Chiplet Design and Heterogeneous Integration Packaging;2023

2. Recent Advances and Trends in Advanced Packaging;IEEE Transactions on Components, Packaging and Manufacturing Technology;2022-02

3. Fan-In Wafer/Panel-Level Chip-Scale Packages;Semiconductor Advanced Packaging;2021

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