1. (1) D. B. Estreich and R. W. Dutton: “Modeling Latch-Up in CMOS Integrated Circuits”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. CAD-I, No. 4, pp. 157-162 (1982)
2. (2) R. C. Baumann: “Radiation-Induced Soft Errors in Advanced Semiconductor Technologies”, IEEE Transactions on Device and Materials Reliability, Vol. 5, No. 3, pp. 305-316 (2005)
3. (3) C.-Y. Tsai, W.-T. Kuo, C.-B. Lin, and T.-L. Chen: “Design and fabrication of MEMS logic gates”, J. Micromech. Microeng., 18, 045001 (10pp) (2008)
4. (4) S. Chakraborty, A. R. Chaudhuri, and T. K. Bhattacharyya: “Design and analysis of MEMS cantilever based binary logic inverter”, in Proc. 2009 Int. Conf. on Advances in Computing, Control, and Telecommunication Technologies, Trivandrum, Kerala, India, pp. 184-188 (2009)
5. (5) T.-H. Lee, S. Bhunia, and M. Mehregany: “Electromechanical Computing at 500 °C with Silicon Carbide”, Science, Vol. 329, Sept. 10, pp. 1316-1318 (2010)