Technical Trend of TSV(Through Silicon Via) Filling for 3D Wafer Electric Packaging-Reference-Cited by-同舟云学术

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Technical Trend of TSV(Through Silicon Via) Filling for 3D Wafer Electric Packaging

Published:2014-06-30 Issue:3 Volume:32 Page:19-26
ISSN:2466-2232
Container-title:Journal of Welding and Joining
language:en
Short-container-title:Journal of Welding and Joining

Author:

Ko Young-Ki,Ko Yong-Ho,Bang Jung-Hwan,Lee Chang-Woo

Publisher

The Korean Welding and Joining Society

Link

http://ocean.kisti.re.kr/downfile/crosscheck/kws/JAKO201421154209026.pdf

Reference11 articles.

1. Study of surface treatment processes for improvement in the wettability of silicon-based materials used in high aspect ratio through-via copper electroplating

2. High aspect ratio copper through-silicon-vias for 3D integration

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Effects of interfacial layer-by-layer nanolayers on the stability of the Cu TSV: Diffusion barrier, adhesion, conformal coating, and mechanical property;Materials Science in Semiconductor Processing;2018-08

2. Effect of Via Pitch on the Extrusion Behavior of Cu-filled TSV;Korean Journal of Metals and Materials;2018-06-05

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