Layout pattern analysis and coverage evaluation in computational lithography

Abstract

In advanced semiconductor technology nodes, the model accuracy of optical proximity correction (OPC) is the key for integrated circuit (IC) chip mask tape out, yield ramp up, and product time-to-market. An accurate model means a small prediction error for the full chip layout. As the full chip layout usually has large pattern variety, an optimal pattern set with good coverage is desired during the model calibration process. Currently, no existing solutions can provide the effective metrics to evaluate the coverage sufficiency of the selected pattern set before a real mask tape out, which may potentially cause higher re-tape out cost and product time-to-market delay due to the multiple rounds of model calibration. In this paper, we construct the metrics to evaluate the pattern coverage before any metrology data is obtained. The metrics are based on either the pattern’s intrinsic, numerical feature representation, or its potential model simulation behavior. Experimental results show a positive correlation between these metrics and lithographic model accuracy. An incremental selection method is also proposed based on the pattern simulation error. It reduces up to 53% of the model’s verification error range. These pattern coverage evaluation methods can improve the efficiency of OPC model building, and are, in turn, beneficial to the whole OPC recipe development process.