Self-tuning Intel Restricted Transactional Memory-Reference-Cited by-同舟云学术

Self-tuning Intel Restricted Transactional Memory

Published:2015-12 Issue: Volume:50 Page:25-52
ISSN:0167-8191
Container-title:Parallel Computing
language:en
Short-container-title:Parallel Computing

Author:

Diegues Nuno,Romano Paolo

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Graphics and Computer-Aided Design,Computer Networks and Communications,Hardware and Architecture,Theoretical Computer Science,Software

Reference76 articles.

1. Transactional memory: architectural support for lock-free data structures;Herlihy,1993

2. Concurrent programming without locks;Fraser;ACM Trans. Comput. Syst.,2007

3. Transactions are tomorrow’s loads and stores;Shavit;Commun. ACM,2008

4. Operating system transactions;Porter,2009

5. Transactional memory support for scalable and transparent parallelization of multiplayer games;Lupei,2010

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Towards an Improved Implementation of Hardware Transactional Memory on Asymmetric Processors;2022 30th Telecommunications Forum (TELFOR);2022-11-15

2. Migration in Hardware Transactional Memory on Asymmetric Multiprocessor;IEEE Access;2021

3. Hardware Transactional Memory Based on Abort Prediction and Adaptive Retry Policy for Multi-Core In-Memory Databases;2018 IEEE International Conference on Big Data and Smart Computing (BigComp);2018-01

4. Seer;ACM Transactions on Computer Systems;2017-12-29

5. Performance Improvement via Always-Abort HTM;2017 26th International Conference on Parallel Architectures and Compilation Techniques (PACT);2017-09