Compiler-assisted power optimization for clustered VLIW architectures-Reference-Cited by-同舟云学术

Compiler-assisted power optimization for clustered VLIW architectures

Published:2011-01 Issue:1 Volume:37 Page:42-59
ISSN:0167-8191
Container-title:Parallel Computing
language:en
Short-container-title:Parallel Computing

Author:

Nagpal Rahul,Srikant Y.N.

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Graphics and Computer-Aided Design,Computer Networks and Communications,Hardware and Architecture,Theoretical Computer Science,Software

Reference43 articles.

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3. A. Azevedo, I. Issenin, R. Cornea, R. Gupta, N. Dutt, A. Veidenbaum, A. Nicolau, Profile-based dynamic voltage scheduling using program checkpoints in the copper framework, in: Proceedings of Design, Automation and Test in Europe Conference (DATE), 2002.

4. R. Balasubramonian, S. Dwarkadas, D.H. Albonesi, Reducing the complexity of the register file in dynamic superscalar processors, in: Proceedings of the International Symposium on Microarchitecture, Washington, DC, USA, 2001, pp. 237–248.

5. Region-based hierarchical operation partitioning for multicluster processors;Chu;SIGPLAN Notices,2003

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3. Improving Energy Efficiency with Dynamic Compiler-Directed Function Unit Power Control;2014 12th IEEE International Conference on Embedded and Ubiquitous Computing;2014-08

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