Author:
Canedo Arquimedes,Abderazek Ben A.,Sowa Masahiro
Subject
Artificial Intelligence,Computer Graphics and Computer-Aided Design,Computer Networks and Communications,Hardware and Architecture,Theoretical Computer Science,Software
Reference48 articles.
1. Design and architecture for an embedded 32-bit QueueCore;Abderazek;Journal of Embedded Computing,2006
2. High-level modeling and FPGA prototyping of produced order parallel queue processor core;Abderazek;Journal of Supercomputing,2006
3. Power-aware compilation for register file reduction;Ayala;International Journal of Parallel Programming,2004
4. Code generation for streaming: an access/execute mechanism;Benitez;SIGARCH Computer Architecture News,1991
5. Exploring a stack architecture;Blake;Computer,1977
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