Testing CMOS combinational iterative logic arrays for realistic faults-Reference-Cited by-同舟云学术

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Testing CMOS combinational iterative logic arrays for realistic faults

Published:1996-12 Issue:3 Volume:21 Page:209-228
ISSN:0167-9260
Container-title:Integration
language:en
Short-container-title:Integration

Author:

Gizopoulos Dimitris,Nikolos Dimitris,Paschalis Antonis

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference15 articles.

1. Testing for faults in cellular logic arrays;Kautz,1967

2. Easily testable iterative systems;Friedman;IEEE Trans. Comput.,1973

3. Tessellation aspects of combinational cellular array testing;Sung;IEEE Trans. Comput.,1974

4. Truth-table verification of an iterative logic array;Dias;IEEE Trans. Comput.,1976

5. A testable design of iterative logic arrays;Parthasarathy;IEEE Trans. Comput.,1981

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Effective design-for-testability techniques for H.264 all-binary integer motion estimation;IET Circuits, Devices & Systems;2010

2. Built-in sequential fault self-testing of array multipliers;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2005-03

3. An effective BIST architecture for sequential fault testing in array multipliers;Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)

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