A Testable Design of Iterative Logic Arrays-Reference-Cited by-同舟云学术

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A Testable Design of Iterative Logic Arrays

Published:1981-11 Issue:11 Volume:C-30 Page:833-841
ISSN:0018-9340
Container-title:IEEE Transactions on Computers
language:
Short-container-title:IEEE Trans. Comput.

Author:

Parthasarathy ,Reddy

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Computational Theory and Mathematics,Hardware and Architecture,Theoretical Computer Science,Software

Link

http://xplorestaging.ieee.org/ielx5/12/35199/01675714.pdf?arnumber=1675714

Cited by 45 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design of a Self-Reconfigurable Adder for Fault-Tolerant VLSI Architecture;2012 International Symposium on Electronic System Design (ISED);2012-12

2. Recursive Pseudo-Exhaustive Two-Pattern Generation;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2010-01

3. Effective design-for-testability techniques for H.264 all-binary integer motion estimation;IET Circuits, Devices & Systems;2010

4. Design-for-testability techniques for CORDIC design;Microelectronics Journal;2009-10

5. Scalable and bijective cells for C-testable iterative logic array architectures;IET Circuits, Devices & Systems;2009-08-01

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