Author:
Diehl D.,Kitada H.,Maeda N.,Fujimoto K.,Ramaswami S.,Sirajuddin K.,Yalamanchili R.,Eaton B.,Rajagopalan N.,Ding R.,Patel S.,Cao Z.,Gage M.,Wang Y.,Tu W.,Kim S.W.,Kulzer R.,Drucker I.,Erickson D.,Ritzdorf T.,Nakamura T.,Ohba T.
Subject
Electrical and Electronic Engineering,Surfaces, Coatings and Films,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials
Reference3 articles.
1. T. Ohba, 3D Large Scale Integration Technology using Wafer-on-Wafer (WOW) Stacking, IEEE IITC. 12.1 June (2010).
2. S. Ramaswami, et al., Process Integration Considerations for 300mm TSV Manufacturing, IEEE TDMR 9(4) December (2009) 524–528.
3. S. Nakai et al., A 65nm CMOS Technology with a High-Performance and Low-Leakage Transistor, a 0.55μm2 6T-SRAM Cell and Robust Hybrid-ULK/Cu Interconnects for Mobile Multimedia Applications, IEEE IEDM Tech. Dig., 11.3, December (2003).
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