Design and characterization of NULL convention arithmetic logic units

Author:

Bandapati Satish K.,Smith Scott C.

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference15 articles.

1. J. McCardle, D. Chester, Measuring an asynchronous processor’s power and noise, in: Proceedings of the Synopsys User Group Conference, Boston, 2001.

2. Design and characterization of NULL convention self-timed multipliers;Bandapati;IEEE Design and Test of Computers,2003

3. NULL convention multiply and accumulate unit with conditional rounding, scaling, and saturation;Smith;Journal of Systems Architecture,2002

4. S.C. Smith, Design of a NULL convention self-timed divider, in Proceedings of the 2004 International Conference on VLSI, June 2004, pp. 447–453.

5. Optimization of NULL convention self-timed circuits;Smith;Integration, The VLSI Journal,2004

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1. Design and Characterization of a Novel FinFET based NCL Cell Library for High Performance Asynchronous Circuits;International Journal of Electrical and Electronics Research;2023-03-30

2. A dual-rail/single-rail hybrid system using null convention logic circuits;Microelectronics Journal;2022-07

3. Transistor Count Reduction Technique for Clockfree Null-convention Arithmetic Logic Circuits;JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE;2021-12-31

4. Design And Throughput Analysis Of 4 Bit Asynchronous Pipelined Multiplier Using Null Convention Logic;2021 IEEE 2nd International Conference on Applied Electromagnetics, Signal Processing, & Communication (AESPC);2021-11-26

5. Gate Diffusion Input Multi-Threshold Null Convention Logic Circuit Design Approach;2020 International SoC Design Conference (ISOCC);2020-10-21

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