Design And Throughput Analysis Of 4 Bit Asynchronous Pipelined Multiplier Using Null Convention Logic
Author:
Affiliation:
1. Institute of Technology, Nirma University,Electronics & Communication Engineering Department,Ahmedabad,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9708066/9708067/09708509.pdf?arnumber=9708509
Reference8 articles.
1. A novel NULL Convention Logic (NCL) Gates Architecture based on Basic Gates;oliveira;2017 IEEE XXIV Int Conf Electron Electr Eng Comput,2017
2. Null convention logic (NCL) based asynchronous design — fundamentals and recent advances
3. Design of Gate Mapping Automation for Asynchronous Null Convention Logic Circuits;ahmed;Int J Sci Eng Technol Res,2014
4. Area performance tradeoffs in NCL multipliers using two-dimensional pipelining;kim;ISOCC 2015 - Int SoC Des Conf SoC Internet Everything,2016
5. Optimization of NULL convention self-timed circuits
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1. Mitigating soft errors in NCL circuits using a transmission gate;Analog Integrated Circuits and Signal Processing;2022-12-20
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