Fluid–structure interaction analysis on the effect of chip stacking in a 3D integrated circuit package with through-silicon vias during plastic encapsulation-Reference-Cited by-同舟云学术

Fluid–structure interaction analysis on the effect of chip stacking in a 3D integrated circuit package with through-silicon vias during plastic encapsulation

Published:2014-01 Issue: Volume:113 Page:40-49
ISSN:0167-9317
Container-title:Microelectronic Engineering
language:en
Short-container-title:Microelectronic Engineering

Author:

Ong Ernest E.S.,Abdullah M.Z.,Khor C.Y.,Loh W.K.,Ooi C.K.,Chan R.

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference25 articles.

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2. M. Koyanagi, in: IEEE International Reliability Physics Symposium (2011) 3F.1.1–1 3F.1.7.

3. International Technology Roadmap for Semiconductor (ITRS), Chapter 6: 3D interconnect metrology, Table MET6, 2011 edition, 18

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