Author:
Chen Shih-Hung,Ker Ming-Dou
Subject
Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials
Reference8 articles.
1. The Art of Analog Layout;Hastings,2001
2. TSMC. 0.25-μm Mixed Signal Salicide Process Design Rule. Taiwan, 2002.
3. VIS. 0.25-μm Logic Salicide Process Design Rule. Taiwan, 2003.
4. UMC. 0.35-μm High Voltage Process Topological Layout Rule. Taiwan, 2002.
5. ESD protection design to overcome internal damages on interface circuits of CMOS IC with multiple separated power pins;Ker;IEEE Trans. Component and Package Technologies,2004
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